Using FPGA to Realize OSD Design in Video Application

OSD FPGA receives OSD data and control commands from DSP DM6-3 through EMIFA, receives video data through video port 1 of DSP, superimposes OSD information on video data, and outputs it to video encoder SAA7105. The functional modules of the OSD are described as follows.

The data port of the address decoding Module interfaces with the lower 32-bit data of EMIFA of DSP DM6?3, and receives the data and control information sent by DM6?3. These data and control information are the original 32-bit data sent by DM6?3. The address decoding module puts the received OSD data, such as the content of the OSD, into the internal FIFO of the FPGA in a 32-bit data format. The control information mainly controls the OSD through a group of control registers.

There are also video interface modules directly connected to the DSP. The video interface module is connected with the video port 2 of the DSP, and stores the data and control information from the video port of the DSP. These control information are directly transmitted to the OSD multiplex control module, and the control information also directly controls the video decoder SAA7105.

The OSD control logic outputs the control information obtained from the control register group to each functional module of the OSD to realize the control of the OSD. The register group is mainly divided into two parts: one is the asynchronous register group, which sends control information such as reset, OSD enable and data width selection to the OSD; the other is the synchronous register group, which mainly controls the position information of the OSD.

The OSD decoding module takes out the data to be displayed from the FIFO according to the control information of the control logic, and outputs it to the OSD CLUT module in a synchronized manner with the video data. The data obtained from the FIFO is the original DSP 32-bit data, and the data required by the OSD CLUT module is 8/16-bit, so the OSD unpacking module needs to unpack the 32-bit data according to certain rules, at the frequency of the video port. Transfer 32-bit data to the OSD CLUT module with a width of 8/16.

Another function of the FIFO module is to pass FIFO status information, such as FIFO full or FIFO empty, to the DMA event generator module. The DMA event generator monitors these events, and if they occur, they are sent to DM6-3 in an interrupted mode to implement correct read and write operations to the FIFO.

The OSD CLUT module finds the corresponding value of YCbCr for the data of each pixel received from the OSD unpacking module, and controls the output order of these OSD CLUT data. This conversion relationship is transmitted by the DSP through the 24-bit data port. The data of the OSD CLUT module is directly output to the OSD multiplexer module.

The OSD multi-channel control module determines the output video data according to the Alpha control bit received from the OSD CLUT module. If the current OSD information, that is, the Alpha control bit is valid, outputs the OSD data to the data conversion module. Otherwise, the original video data received from the video interface module is output to realize the OSD function.

The data output by the OSD multi-channel controller is not directly sent to the video decoder, but through the data conversion module, according to the specific application conditions, the necessary data format conversion is performed. It can be seen from the interface timing of SAA7105 that when SAA7105 is configured as composite video output, the required data is single clock edge data. At this time, the data conversion module does not do any work, and the data received from the OSD multi-channel control module is transmitted intact. For SAA7105; if SAA7105 is configured as VGA or HDTV output mode, dual clock edge data is required, then the data conversion module converts the single clock edge data received from the OSD controller into dual clock edge data, and outputs it to the video decoder SAA7105 .

It can be seen that the FPGA has completed all the work of the OSD. If you want to Display the OSD content, DM6?3 only needs to send control commands to the FPGA through the EMFIA port. These commands of course include the OSD content and location information.

OSD control

The OSD design implemented by the XC3S250E displays the OSD according to the received OSD location and content information, without any restrictions on the content displayed by the OSD, which is very flexible and convenient. The following describes the control operation of the OSD by taking the display of Chinese characters on the OSD as an example.

To display Chinese characters correctly, it is necessary to convert the input Chinese character internal code into the corresponding location code. For this function, we pass the function Uint32 Code_Converse(unsigned char *CodeNPointer), whose input is a pointer, pointing to the Chinese characters to be converted. The return value is the area code corresponding to the Chinese character. The display of OSD is realized by the function OSDHZ?display:

  		void OSDHZ_ Display

{

Uint8 *pFrame

Uint32 pitch

OSDUTIL_Point* loc

Uint32 CodeQ

OSDHZ?ont *font

Uint8 fgColor

Uint8 bgColor

}

Among them, Uint8 *pFrame is the Buffer buffer output by OSD; Uint32 pitch is the pixel value displayed in each line; OSDUTIL_Point *loc is the display position of the first character; Uint32 CodeQ is the location code of the Chinese character to be displayed; OSDHZ?ont * font is the font used to display Chinese characters; Uint8 fgColor displays the foreground color of Chinese characters; Uint8 bgColor displays the background color of Chinese characters.

Therefore, if you need to display Chinese characters, you only need to convert the Chinese characters to the necessary code system, and then output the converted area code to the OSD FPGA to give the displayed position. Of course, to display Chinese characters, a Chinese character library is essential.

author:

Li Hongshuai

design engineer

Beijing Hezhongda Electronic Technology Co., Ltd.